NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 663 / 1359

• 12-bit resolution
• Designed for maximum ADC clock frequency of 25 MHz with 40 ns period
• Sampling rate up to 8.83 million samples per second
1
• Single conversion time of 8.5 ADC clock cycles (8.5 × 40 ns =340 ns)
• Additional conversion time of 6 ADC clock cycles (6 × 40 ns = 240 ns)
• Eight conversions in 26.5 ADC clock cycles (26.5 × 40 ns = 1.060 µs) using parallel
mode
• Can be synchronized to other peripherals that are connected to an internal Inter-
Peripheral Crossbar module and PDB, such as the PWM, through the SYNC0/1 input
signal
• Sequentially scans and stores up to sixteen measurements
• Scans and stores up to eight measurements each on two ADC converters operating
simultaneously and in parallel
• Scans and stores up to eight measurements each on two ADC converters operating
asynchronously to each other in parallel
• A scan can pause and await new SYNC input prior to continuing
• Gains the input signal by x1, x2, or x4
• Optional interrupts at end of scan if an out-of-range limit is exceeded or there is a
zero crossing
• Optional DMA function to transfer conversion data at the end of a scan or when a
sample is ready to be read.
• Optional sample correction by subtracting a pre-programmed offset value
• Signed or unsigned result
• Single-ended or differential inputs
• PWM outputs with hysteresis for three of the analog inputs
1. In loop mode, the time between each conversion is 6 ADC clock cycles (240 ns). Using simultaneous conversion,
two samples can be obtained in 240 ns. Samples per second is calculated according to 240 ns per two samples or
8,333,333 samples per second.
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
663