NXP Semiconductors freescale KV4 Series, Reference Manual

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Clock name Description
Fast Peripheral clock MCGOUTCLK divided by OUTDIV2 clocks the UARTs, SPI,
eFlexPWM, FTMs, PDBs, ENC, FlexCAN, XBARA, and ADC
modules.
Bus /Flash clock MCGOUTCLK divided by OUTDIV4 clocks Flash, I2C,
WDOG, EWM, PIT, LPTIMER , OSC, MCG, PMC , XBARB/
AOI, CMP.
MCGIRCLK MCG output of the slow or fast internal reference clock
MCGFFCLK MCG output of the slow internal reference clock or a divided
MCG external reference clock.
MCGOUTCLK MCG output of either IRC, MCGPLLCLK, or MCG's external
reference clock that sources the core, system, bus and flash
clocks. It is also an option for the debug trace clock.
MCGPLLCLK MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may
clock some modules.
MCGPLL2XCLK MCG output of PLL. Two time faster than MCGPLLCLK, used
as nanoedge 2x clock source.
OSCCLK System oscillator output of the internal oscillator or sourced
directly from EXTAL
OSCERCLK System oscillator output sourced from OSCCLKthat may
clock some on-chip modules
LPO PMC 1kHz output
6.3 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. Each
divider is programmable from a divide-by-1 through divide-by-16 setting. The following
requirements must be met when configuring the clocks for this device:
1. The System clock frequency that drives the CPU platform must be 150 MHz or
slower in HSRUN mode, or 100MHZ or slower in normal RUN mode.
2. The fast peripheral bus clock frequency must be an integer divide or multiple of the
core/system clock. ie x2,x3,x4 or divide by 2/4/8. This allows key peripherals can be
clocked at high speed, while core/System is running slower to conserve power
consumption
3. The (slow peripheral) bus flash clock must not exceed 25MHz, and be an integer
divide of the core/System clock and an integer divide of the fast peripheral clock.
4. The nanoedge module requires two clock inputs, where one clock input is 2x the
other clock frequency. Thus the fast peripheral bus clock provides the nanoedge
clock, and MCGPLLCLK or MCGPLL2XCLK provides the "2x Fast peripheral bus
clock" . Each of these clocks must be an integer divide or multiple of the System
clock. The nanoedge module is expected to be programmed to use clock inputs of
75/150MHZ, 100/200MHZ, and possible 120/240MHZ to support sub-nanosecond
resolution control of the flexPWM.
Chapter 6 Clock Distribution
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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