Table 2-2. Core modules (continued)
Module
Description
Most of this device's debug is based on the ARM CoreSight
™
architecture. Four
debug interface is supported:
• JTAG Controller (JTAG)
• IEEE 1149.7 JTAG (cJTAG)
• Serial Wire Debug (SWD)
• ARM Real-Time Trace Interface
2.2.2 System Modules
The following system modules are available on this device.
Table 2-3. System modules
Module
Description
System integration module (SIM)
The SIM includes integration logic and several module configuration settings.
The SMC provides control and protection on entry and exit to each power mode,
control for the Power management controller (PMC), and reset entry and exit for
the complete MCU.
Power management controller (PMC)
The PMC provides the user with multiple power options. Ten different modes are
supported that allow the user to optimize power consumption for the level of
functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Low-leakage wakeup unit (LLWU)
The LLWU module allows the device to wake from low leakage power modes
(VLLSx) through various internal peripheral and external pin sources.
Miscellaneous control module (MCM)
The MCM includes integration logic and embedded trace buffer details.
The XBS connects bus masters and bus slaves, allowing all bus masters to access
different bus slaves simultaneously and providing arbitration among the bus
masters when they access the same slave.
The peripheral bridge converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
The DMA multiplexer selects from many DMA requests down to a smaller number
for the DMA controller.
Direct memory access (DMA) controller
The DMA controller provides programmable channels with transfer control
descriptors for data movement via dual-address transfers for 8-, 16-, 32-, 128-, and
256-bit data values.
External watchdog monitor (EWM)
The EWM is a redundant mechanism to the software watchdog module that
monitors both internal and external system operation for fail conditions.
The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 KHz low power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
Inter-Peripheral Crossbar (XBARA/
XBARB)
Provides generalized connections between and among on-chip peripherals: Cyclic
ADC, 12-bit DAC, Comparators, Timers, eFlexPWMs, PDBs, EWM, Quadrature
Decoder, and select I/O pins. AND-OR-INVERT function that provides a universal
Boolean function generator using a four-term sum-of-products expression, with
Chapter 2 Introduction
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
65
Summary of Contents for freescale KV4 Series
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