NXP Semiconductors freescale KV4 Series, Reference Manual

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PDB
counter
MOD, IDLY
0
DACINT x
DACINT x x3
DACINT x x2
... ...
CH n DLY1
CH n DLY0
DAC internal trigger x
Ch n pre-trigger 0
Ch n pre-trigger 1
Ch n trigger
PDB interrupt
... ...
Trigger input event
Figure 38-81. PDB ADC triggers and DAC interval triggers use case
NOTE
Because the DAC interval counters share the prescaler with
PDB counter, PDB must be enabled if the DAC interval trigger
outputs are used in the applications.
38.5.4 Pulse-Out's
PDB can generate pulse outputs of configurable width. When PDB counter reaches the
value set in POyDLY[DLY1], the Pulse-Out goes high; when the counter reaches
POyDLY[DLY2], it goes low. POyDLY[DLY2] can be set either greater or less than
POyDLY[DLY1].
ADC pre-trigger/trigger outputs and Pulse-Out generation have the same time base,
because they both share the PDB counter.
The pulse-out connections implemented in this MCU are described in the device's chip
configuration details.
38.5.5 Updating the delay registers
The following registers control the timing of the PDB operation; and in some of the
applications, they may need to become effective at the same time.
Chapter 38 Programmable Delay Block (PDB)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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