NXP Semiconductors freescale KV4 Series, Reference Manual

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SIM_SCGC6 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
0
FTF
Flash Memory Clock Gate Control
This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory
is clock gated, but entry into low power modes is blocked.
0 Clock disabled
1 Clock enabled
13.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)
Address: 4004_7000h base + 1040h offset = 4004_8040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DMA
0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
SIM_SCGC7 field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
DMA
DMA Clock Gate Control
This bit controls the clock gate to the DMA module.
0 Clock disabled
1 Clock enabled
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
13.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)
When updating CLKDIV1, update all fields using the one write command. Attempting to
write an invalid clock ratio to the CLKDIV1 register will cause the write to be ignored.
The maximum divide ratio that can be programmed between core/system clock and the
other divided clocks is divide by 8. When OUTDIV1 equals 0000 (divide by 1), the other
dividers cannot be set higher than 0111 (divide by 8).
Memory map and register definition
KV4x Reference Manual, Rev. 2, 02/2015
194
Preliminary
Freescale Semiconductor, Inc.