NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1112 / 1359

Address: Base a 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
BOFFDONEMSK
0 0
RFFN TASD MRP RRS
EACEN
W
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_CTRL2 field descriptions
Field Description
31
Reserved
This field is reserved.
30
BOFFDONEMSK
Bus Off Done Interrupt Mask
This bit provides a mask for the Bus Off Done Interrupt in CAN_ESR1 register.
0 Bus Off Done interrupt disabled.
1 Bus Off Done interrupt enabled.
29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
RFFN
Number Of Rx FIFO Filters
This 4-bit field defines the number of Rx FIFO filters, as shown in the following table. The maximum
selectable number of filters is determined by the MCU. This field can only be written in Freeze mode as it
is blocked by hardware in other modes. This field must not be programmed with values that make the
number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of Mailboxes present,
defined by CAN_MCR[MAXMB].
NOTE: Each group of eight filters occupies a memory space equivalent to two Message Buffers which
means that the more filters are implemented the less Mailboxes will be available.
Considering that the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN
should be programmed with a value corresponding to a number of filters not greater than the
number of available memory words which can be calculated as follows:
Table continues on the next page...
Memory map/register definition
KV4x Reference Manual, Rev. 2, 02/2015
1112
Preliminary
Freescale Semiconductor, Inc.