NXP Semiconductors freescale KV4 Series, Reference Manual

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CANx_CTRL2 field descriptions (continued)
Field Description
(SETUP_MB - 6) × 4
where SETUP_MB is the least between the parameter NUMBER_OF_MB and
CAN_MCR[MAXMB].
The number of remaining Mailboxes available will be:
(SETUP_MB - 8) - (RFFN × 2)
If the Number of Rx FIFO Filters programmed through RFFN exceeds the SETUP_MB value
(memory space available) the exceeding ones will not be functional.
NOTE:
• The number of the last remaining available mailboxes is defined by the least value between
the NUMBER_OF_MB minus 1 and the CAN_MCR[MAXMB] field.
• If Rx Individual Mask Registers are not enabled then all Rx FIFO filters are affected by the
Rx FIFO Global Mask.
RFFN[3:
0]
Number
of Rx
FIFO filter
elements
Message
Buffers
occupied by Rx
FIFO and ID
Filter Table
Remaining
Available
Mailboxes
Rx FIFO ID Filter
Table Elements
Affected by Rx
Individual Masks
Rx FIFO ID Filter
Table Elements
Affected by Rx
FIFO Global Mask
0x0 8 MB 0-7 MB 8-63 Elements 0-7 none
0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15
0x2 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23
0x3 32 MB 0-13 MB 14-63 Elements 0-13 Elements 14-31
0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47
0x6 56 MB 0-19 MB 20-63 Elements 0-19 Elements 20-55
0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71
0x9 80 MB 0-25 MB 26-63 Elements 0-25 Elements 26-79
0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements 28-87
0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95
0xC 104 MB 0-31 MB 32-63 Elements 0-31 Elements 32-103
0xD 112 MB 0-33 MB 34-63 Elements 0-31 Elements 32-111
0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119
0xF 128 MB 0-37 MB 38-63 Elements 0-31 Elements 32-127
23–19
TASD
Tx Arbitration Start Delay
This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the
first bit of CRC field on CAN bus. See
Tx Arbitration start delay for more details. This field can be written
only in Freeze mode because it is blocked by hardware in other modes.
18
MRP
Mailboxes Reception Priority
If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching
continues on the Rx FIFO. This bit can be written only in Freeze mode because it is blocked by hardware
in other modes.
Table continues on the next page...
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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