NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 702 / 1359

ADC_SCTRL field descriptions (continued)
Field Description
0 Perform sample immediately after the completion of the current sample.
1 Delay sample until a new sync input occurs.
34.4.24 ADC Power Control Register (ADC_PWR2)
Address: 4005_C000h base + A6h offset = 4005_C0A6h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0
DIV1
0
SPEEDB SPEEDA
Write
Reset
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
ADC_PWR2 field descriptions
Field Description
15–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13–8
DIV1 Clock Divisor Select
The divider circuit operates in the same manner as the CTRL2[DIV0] field but is used to generate the
clock used by ADCB during parallel non-simultaneous scan modes.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–2
SPEEDB
ADCB Speed Control Bits
These bits configure the clock speed at which the ADCB can operate. Faster conversion speeds require
greater current consumption.
00 Conversion clock frequency ≤ 6.25 MHz; current consumption per converter = 6 mA
01 Conversion clock frequency ≤ 12.5 MHz; current consumption per converter = 10.8 mA
10 Conversion clock frequency ≤ 18.75 MHz; current consumption per converter = 18 mA
11 Conversion clock frequency ≤ 25 MHz; current consumption per converter = 25.2 mA
SPEEDA ADCA Speed Control Bits
These bits configure the clock speed at which the ADCA can operate. Faster conversion speeds require
greater current consumption.
00 Conversion clock frequency ≤ 6.25 MHz; current consumption per converter = 6 mA
01 Conversion clock frequency ≤ 12.5 MHz; current consumption per converter = 10.8 mA
10 Conversion clock frequency ≤ 18.75 MHz; current consumption per converter = 18 mA
11 Conversion clock frequency ≤ 25 MHz; current consumption per converter = 25.2 mA
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
702
Preliminary
Freescale Semiconductor, Inc.