NXP Semiconductors freescale KV4 Series, Reference Manual

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T = DEADTIME INTERVAL BEFORE ASSERTION OF TOP PWM
B = DEADTIME INTERVAL BEFORE ASSERTION OF BOTTOM PWM
V+
DEADTIME
B B T T
POSITIVE
CURRENT
PWM TO TOP
TRANSISTOR
PWM TO BOTTOM
TRANSISTOR
LOAD VOLTAGE WITH
HIGH POSITIVE CURRENT
LOAD VOLTAGE WITH
LOW POSITIVE CURRENT
LOAD VOLTAGE WITH
HIGH NEGATIVE CURRENT
LOAD VOLTAGE WITH
LOW NEGATIVE CURRENT
NEGATIVE
CURRENT
Figure 37-244. Output Voltage Waveforms
37.5.2.9 Fractional Delay Logic
For applications where more resolution than a single IPBus clock period is needed, the
fractional delay logic can be used to achieve fine resolution on the rising and falling
edges of the PWM_A and PWM_B outputs and fine resolution for the PWM period.
Enable the use of the fractional delay logic by setting FRCTRL[FRACx_EN]. The
FRACVALx registers act as a fractional clock cycle addition to the turn on and turn off
count specified by the VAL2, VAL3, VAL4, or VAL5 registers. The FRACVAL1
register acts as a fractional increase in the PWM period as defined by VAL1. If
FRACVAL1 is programmed to a non-zero value, then the largest value for the VAL1
register is 0xFFFE for unsigned usage or 0x7FFE for signed usage. This limit is needed
in order to avoid counter rollovers when accumulating the fractional additional period.
The results of the fractional delay logic depend on whether or not the PWM submodule
has an analog micro-edge placer block available.
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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