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MCG_C6 field descriptions (continued)
Field
Description
0
No interrupt request is generated on loss of lock.
1
Generate an interrupt request on loss of lock.
6
PLLS
PLL Select
Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS
bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is
disabled in all modes.
0
FLL is selected.
1
PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference
clock in the range of 8–16 MHz prior to setting the PLLS bit).
5
CME0
Clock Monitor Enable
Enables the loss of clock monitoring circuit for the OSC0 external reference mux select. The LOCRE0 bit
will determine if a interrupt or a reset request is generated following a loss of OSC0 indication. The CME0
bit must only be set to a logic 1 when the MCG is in an operational mode that uses the external clock
(FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, the value of the RANGE0
bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters
any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a
logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
0
External clock monitor is disabled for OSC0.
1
External clock monitor is enabled for OSC0.
VDIV
VCO Divider
Selects the amount to divide the VCO output of the PLL. The VDIV bits establish the multiplication factor
(M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN or
PLLS), the VDIV value must not be changed when LOCK is zero.
Table 30-9. PLL VCO Divide Factor
VDIV
Multiply
Factor
VDIV
Multiply
Factor
VDIV
Multiply
Factor
VDIV
Multiply
Factor
00000
16
01000
24
10000
32
11000
40
00001
17
01001
25
10001
33
11001
41
00010
18
01010
26
10010
34
11010
42
00011
19
01011
27
10011
35
11011
43
00100
20
01100
28
10100
36
11100
44
00101
21
01101
29
10101
37
11101
45
00110
22
01110
30
10110
38
11110
46
00111
23
01111
31
10111
39
11111
47
Memory Map/Register Definition
KV4x Reference Manual, Rev. 2, 02/2015
556
Preliminary
Freescale Semiconductor, Inc.
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