NXP Semiconductors freescale KV4 Series, Reference Manual

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9.9 DWT
The DWT is a unit that performs the following debug functionality:
• It contains four comparators that you can configure as a hardware watchpoint, a PC
sampler event trigger, or a data address sampler event trigger. The first comparator,
DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The
second comparator, DWT_COMP1, can also be used as a data comparator.
• The DWT contains counters for:
• Clock cycles (CYCCNT)
• Folded instructions
• Load store unit (LSU) operations
• Sleep cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
NOTE
An event is emitted each time a counter overflows.
• The DWT can be configured to emit PC samples at defined intervals, and to emit
interrupt event information.
9.10 Debug in Low Power Modes
In low power modes in which the debug modules are kept static or powered off, the
debugger cannot gather any debug data for the duration of the low power mode. In the
case that the debugger is held static, the debug port returns to full functionality as soon as
the low power mode exits and the system returns to a state with active debug. In the case
that the debugger logic is powered off, the debugger is reset on recovery and must be
reconfigured once the low power mode is exited.
Power mode entry logic monitors Debug Power Up and System Power Up signals from
the debug port as indications that a debugger is active. These signals can be changed in
RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to
enter stop or VLPS, FCLK continues to run to support core register access. In these
modes in which FCLK is left active the debug modules have access to core registers but
not to system memory resources accessed via the crossbar.
DWT
KV4x Reference Manual, Rev. 2, 02/2015
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Preliminary
Freescale Semiconductor, Inc.