NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1288 / 1359

UARTx_MODEM field descriptions (continued)
Field Description
0 The receiver has no effect on RTS.
1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or
greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver
data register (FIFO) is less than RWFIFO[RXWATER]. See
Hardware flow control
2
TXRTSPOL
Transmitter request-to-send polarity
Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the polarity of the receiver RTS.
RTS will remain negated in the active low state unless TXRTSE is set.
0 Transmitter RTS is active low.
1 Transmitter RTS is active high.
1
TXRTSE
Transmitter request-to-send enable
Controls RTS before and after a transmission.
0 The transmitter has no effect on RTS.
1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the
start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer
and shift register are completely sent, including the last stop bit. (FIFO)(FIFO)
0
TXCTSE
Transmitter clear-to-send enable
TXCTSE controls the operation of the transmitter. TXCTSE can be set independently from the state of
TXRTSE and RXRTSE.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send
a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in
the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is
being sent do not affect its transmission.
Memory map and registers
KV4x Reference Manual, Rev. 2, 02/2015
1288
Preliminary
Freescale Semiconductor, Inc.