NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 201 / 1359

13.2.20 System Clock Divider Register 4 (SIM_CLKDIV4)
Address: 4004_7000h base + 1068h offset = 4004_8068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRACEDIVEN
0
W
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TRACEDIV
TRACEFRAC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_CLKDIV4 field descriptions
Field Description
31–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
TRACEDIVEN
Debug Trace Divider Control
This bit controls the Debug Trace Divider.
0 Debug trace divider disabled
1 Debug trace divider enabled
27–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–1
TRACEDIV
Trace clock divider divisor
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the fractional clock divider is set by the SOPT2 TRACECLKSEL register bit. Divider output clock
= Divider input clock * ((TR1)/(T1))
0
TRACEFRAC
Trace clock divider fraction
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source
clock for the fractional clock divider is set by the SOPT2 TRACECLKSEL register bit. Divider output clock
= Divider input clock*((TR1)/(T1))
Chapter 13 System Integration Module (SIM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
201