NXP Semiconductors freescale KV4 Series, Reference Manual

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SPI_CTARn field descriptions (continued)
Field Description
10 Delay after Transfer Prescaler value is 5.
11 Delay after Transfer Prescaler value is 7.
19–18
PDT
Delay after Transfer Prescaler
Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and
the assertion of PCS at the beginning of the next frame. The PDT field is only used in master mode. See
the DT field description for details on how to compute the Delay after Transfer. Refer
Delay after Transfer
(t
DT
) for more details.
00 Delay after Transfer Prescaler value is 1.
01 Delay after Transfer Prescaler value is 3.
10 Delay after Transfer Prescaler value is 5.
11 Delay after Transfer Prescaler value is 7.
17–16
PBR
Baud Rate Prescaler
Selects the prescaler value for the baud rate. This field is used only in master mode. The baud rate is the
frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection
takes place. See the BR field description for details on how to compute the baud rate.
00 Baud Rate Prescaler value is 2.
01 Baud Rate Prescaler value is 3.
10 Baud Rate Prescaler value is 5.
11 Baud Rate Prescaler value is 7.
15–12
CSSCK
PCS to SCK Delay Scaler
Selects the scaler value for the PCS to SCK delay. This field is used only in master mode. The PCS to
SCK Delay is the delay between the assertion of PCS and the first edge of the SCK. The delay is a
multiple of the protocol clock period, and it is computed according to the following equation:
t
CSC
= (1/f
P
) x PCSSCK x CSSCK.
The following table lists the delay scaler values.
Table 44-14. Delay Scaler Encoding
Field Value Delay Scaler Value
0000 2
0001 4
0010 8
0011 16
0100 32
0101 64
0110 128
0111 256
1000 512
1001 1024
1010 2048
1011 4096
1100 8192
Table continues on the next page...
Memory Map/Register Definition
KV4x Reference Manual, Rev. 2, 02/2015
1186
Preliminary
Freescale Semiconductor, Inc.