NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 661 / 1359

Chapter 34
12-bit Cyclic Analog-to-Digital Converter (ADC)
Chip-specific Cyclic ADC information
34.1.1 Cyclic ADC Instantiation
It is a dual ADC. The signals of its first ADC are labeled A, as in ANA, ADCA,
VREFLA, and VREFHA. The signals of its second ADC are labeled B, as in ANB,
ADCB, VREFLB, and VREFHB.
34.1.2 Cyclic ADC SYNC Signal Connections
XBARA_OUT12 and PDB0 channel trigger outputs can trigger ADCA and ADCB
(parallel sampling) conversion via SYNC0 input. XBARA_OUT13 and PDB1 channel
trigger outputs can trigger ADCB conversions via SYNC1 input.
Each ADC can be synchronized to another module, such as a PWMA, through the
XBARA connections.
Each ADC can be synchronized to PDB0/1 trigger input with a programmable delay
through the PDB0/1 connections.
See SIM_SOPT7 and PDB0 Input Trigger Connections .
34.1
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
661