NXP Semiconductors freescale KV4 Series, Reference Manual

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34.6 Reset
At reset, all the registers return to the reset state.
34.7 Clocks
The ADC has two external clock inputs to drive two clock domains within the ADC
module.
Table 34-96. Clock Summary
Clock input Source Characteristics
IP Clock SIM
Maximun rate is 150 MHz from fast bus clock domain. When the device is
in low power mode, the IP clock is from MCGIRCLK.
RC Clock MCG
MCG provides MCGIRCLK for auto standby power saving mode.
MCGIRCLK must be configured to 4 MHz before ADC enters low power
mode.
The IP clock is sourced by fast bus clock and the maximum rate is 150 MHz.
The IP_CLK is enabled only when the SIM_SCGC5[ADC] bit is set. This clock enable
bit must be set before the ADC can be used.
The conversion clock is the primary source for the ADC clock and is always selected as
the ADC clock when conversions are in process. The ADC clock is sourced by fast bus
clock in normal mode and MCGIRC in stop mode,, and CTRL2[DIV0] and
PWR2[DIV1] should be configured so that conversion clock frequency falls between 100
kHz and 25 MHz. Operating the ADC at out-of-spec conversion clock frequencies or
reconfiguring the parameters that affect clock rates or power modes while the regulators
are powered up (PWR[PD0]=0 or PWR[PD1]=0) negatively affects conversion accuracy.
The conversion clock that the ADC uses for sampling is calculated using the IP bus clock
and the clock divisor bits within the ADC Control Register 2. The ADC clock is active
100 percent of the time in looping modes or in normal power mode. It is also active
during all ADC powerup sequences for a period of time determined by the
PWR[PUDELAY] field. If a conversion is initiated in power savings mode, then the
ADC clock continues until the conversion sequence completes.
The following diagram shows the structure of the clocking system.
Reset
KV4x Reference Manual, Rev. 2, 02/2015
718
Preliminary
Freescale Semiconductor, Inc.