For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles
(9 bit times × 16 RT 10 RT cycles).
With the misaligned character shown in the
, the receiver counts 154 RT
cycles at the point when the count of the transmitting device is 160 RT cycles (10 bit
times × 16 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a fast 8-bit character with no errors is:
((154 − 160) ÷ 154) × 100 = 3.90%
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles
(10 bit times × 16 RT 10 RT cycles).
With the misaligned character shown in the
, the receiver counts 170 RT
cycles at the point when the count of the transmitting device is 176 RT cycles (11 bit
times × 16 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit character with no errors is:
((170 − 176) ÷ 170) × 100 = 3.53%
46.5.2.9 Receiver wakeup
C1[WAKE] determines how the UART is brought out of the standby state to process an
incoming message. C1[WAKE] enables either idle line wakeup or address mark wakeup.
46.5.2.9.1 Idle input line wakeup (C1[WAKE] = 0)
In this wakeup method, an idle condition on the unsynchronized receiver input signal
clears C2[RWU] and wakes the UART. The initial frame or frames of every message
contain addressing information. All receivers evaluate the addressing information, and
receivers for which the message is addressed process the frames that follow. Any receiver
for which a message is not addressed can set its C2[RWU] and return to the standby state.
C2[RWU] remains set and the receiver remains in standby until another idle character
appears on the unsynchronized receiver input signal.
Idle line wakeup requires that messages be separated by at least one idle character and
that no message contains idle characters.
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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