NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1310 / 1359

RECEIVER
RT CLOCK
MSB STOP
DATA
SAMPLES
RT
16
RT
15
RT
14
RT
13
RT1
2
RT
11
RT1
0
RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1
Figure 46-75. Slow data
For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles
(9 bit times × 16 RT 10 RT cycles).
With the misaligned character shown in the Figure 46-75 , the receiver counts 154 RT
cycles at the point when the count of the transmitting device is 147 RT cycles (9 bit times
× 16 RT 3 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a slow 8-bit data character with no errors is:
((154 − 147) ÷ 154) × 100 = 4.54%
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles
(10 bit times × 16 RT 10 RT cycles).
With the misaligned character shown in the Figure 46-75 , the receiver counts 170 RT
cycles at the point when the count of the transmitting device is 163 RT cycles (10 bit
times × 16 RT 3 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a slow 9-bit character with no errors is:
((170 − 163) ÷ 170) × 100 = 4.12%
46.5.2.8.2 Fast data tolerance
The following figure shows how much a fast received frame can be misaligned. The fast
stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
RECEIVER
RT CLOCK
STOP IDLE OR NEXT FRAME
DATA
SAMPLES
RT
16
RT
15
RT
14
R
T
13
RT1
2
RT
11
R
T1
0
R
T9
R
T8
R
T7
R
T6
R
T5
R
T4
R
T3
R
T2
R
T1
Figure 46-76. Fast data
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
1310
Preliminary
Freescale Semiconductor, Inc.