NXP Semiconductors freescale KV4 Series, Reference Manual

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43.4.15 Rx FIFO Global Mask register (CANx_RXFGMASK)
This register is located in RAM.
If Rx FIFO is enabled, RXFGMASK is used to mask the Rx FIFO ID Filter Table
elements that do not have a corresponding RXIMR according to CAN_CTRL2[RFFN]
field setting.
This register can only be written in Freeze mode as it is blocked by hardware in other
modes.
Address: Base a 48h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FGM
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
CANx_RXFGMASK field descriptions
Field Description
FGM Rx FIFO Global Mask Bits
These bits mask the ID Filter Table elements bits in a perfect alignment.
The following table shows how the FGM bits correspond to each IDAF field.
Rx FIFO ID
Filter Table
Elements
Format
(CAN_MCR[ID
AM])
Identifier Acceptance Filter Fields
RTR IDE RXIDA RXIDB
1
RXIDC
2
Reserved
A FGM[31] FGM[30] FGM[29:1] - - FGM[0]
B FGM[31],
FGM[15] FGM[30],
FGM[14] - FGM[29:16],
FGM[13:0] -
C - - - FGM[31:24],
FGM[23:16],
FGM[15:8],
FGM[7:0]
0 The corresponding bit in the filter is "don’t care."
1 The corresponding bit in the filter is checked.
1. If CAN_MCR[IDAM] field is equivalent to the format B only the fourteen most significant bits of the Identifier of the incoming
frame are compared with the Rx FIFO filter.
2. If CAN_MCR[IDAM] field is equivalent to the format C only the eight most significant bits of the Identifier of the incoming
frame are compared with the Rx FIFO filter.
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1117