NXP Semiconductors freescale KV4 Series, Reference Manual

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RCM_SSRS0 field descriptions (continued)
Field Description
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
SLOL
Sticky Loss-of-Lock Reset
Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for
information on the loss-of-clock event.
0 Reset not caused by a loss of lock in the PLL
1 Reset caused by a loss of lock in the PLL
2
SLOC
Sticky Loss-of-Clock Reset
Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled
for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the
clock monitor.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
SLVD
Sticky Low-Voltage Detect Reset
If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs.
This field is also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
0
SWAKEUP
Sticky Low Leakage Wakeup Reset
Indicates a reset has been caused by an enabled LLWU modulewakeup source while the chip was in a
low leakage mode. Any enabled wakeup source in a VLLSx mode causes a reset.
0 Reset not caused by LLWU module wakeup source
1 Reset caused by LLWU module wakeup source
15.2.6 Sticky System Reset Status Register 1 (RCM_SSRS1)
This register includes status flags to indicate all reset sources since the last POR, LVD or
VLLS Wakeup that have not been cleared by software. Software can clear the status flags
by writing a logic one to a flag.
Address: 4007_F000h base + 9h offset = 4007_F009h
Bit 7 6 5 4 3 2 1 0
Read 0 0 SSACKERR 0 SMDM_AP SSW SLOCKUP 0
Write w1c w1c w1c w1c
Reset
0 0 0 0 0 0 0 0
Reset memory map and register descriptions
KV4x Reference Manual, Rev. 2, 02/2015
262
Preliminary
Freescale Semiconductor, Inc.