NXP Semiconductors freescale KV4 Series, Reference Manual

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PWMA_FSTS field descriptions (continued)
Field Description
These read/write bits are used to control the timing for re-enabling the PWM outputs after a fault condition.
These bits apply to both automatic and manual clearing of a fault condition.
NOTE: Both FHALF and FFULL can be set so that the fault recovery occurs at the start of a full cycle and
at the start of a half cycle (as defined by VAL0). If neither FHALF nor FFULL is set, then no fault
recovery is possible.
0 PWM outputs are not re-enabled at the start of a half cycle.
1 PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
11–8
FFPIN
Filtered Fault Pins
These read-only bits reflect the current state of the filtered FAULTx pins converted to high polarity. A logic
1 indicates a fault condition exists on the filtered FAULTx pin. A reset has no effect on this field.
7–4
FFULL
Full Cycle
These read/write bits are used to control the timing for re-enabling the PWM outputs after a fault condition.
These bits apply to both automatic and manual clearing of a fault condition.
NOTE: Both FHALF and FFULL can be set so that the fault recovery occurs at the start of a full cycle and
at the start of a half cycle (as defined by VAL0). If neither FHALF nor FFULL is set, then no fault
recovery is possible.
0 PWM outputs are not re-enabled at the start of a full cycle
1 PWM outputs are re-enabled at the start of a full cycle
FFLAG Fault Flags
These read-only flag is set within two CPU cycles after a transition to active on the FAULTx pin. Clear this
bit by writing a logic one to it. A reset clears this field. While the reset value is 0, these bits may be set to 1
by the time they can be read depending on the state of the fault input signals.
0 No fault on the FAULTx pin.
1 Fault on the FAULTx pin.
37.4.52 Fault Filter Register (PWMA_FFILT)
The settings in this register are shared among each of the fault input filters within the
fault channel.
Input filter considerations include:
• The FILT_PER value should be set such that the sampling period is larger than the
period of the expected noise. This way a noise spike will only corrupt one sample.
The FILT_CNT value should be chosen to reduce the probability of noisy samples
causing an incorrect transition to be recognized. The probability of an incorrect
transition is defined as the probability of an incorrect sample raised to the
F3 power.
• The values of FILT_PER and FILT_CNT must also be traded off against the desire
for minimal latency in recognizing input transitions. Turning on the input filter
(setting FILT_PER to a non-zero value) introduces a latency of ((F4) x
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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