NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 876 / 1359

PDBx_CNT field descriptions (continued)
Field Description
Contains the current value of the counter.
38.4.4 Interrupt Delay register (PDBx_IDLY)
Address: Base a Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
IDLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDBx_IDLY field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
IDLY PDB Interrupt Delay
Specifies the delay value to schedule the PDB interrupt. It can be used to schedule an independent
interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the counter is
equal to the IDLY. Reading this field returns the value of internal register that is effective for the current
cycle of the PDB.
38.4.5 Channel n Control register 1 (PDBx_CHnC1)
Each PDB channel has one control register, CHnC1. The fields in this register control the
functionality of each PDB channel operation.
Address: Base a 10h (40d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
BB TOS EN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnC1 field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
BB
PDB Channel Pre-Trigger Back-to-Back Operation Enable
Enables the PDB ADC pre-trigger operation as back-to-back mode. Only lower M pre-trigger bits are
implemented in this MCU. Back-to-back operation enables the ADC conversions complete to trigger the
next PDB channel pre-trigger and trigger output, so that the ADC conversions can be triggered on the next
Table continues on the next page...
Memory map and register definition
KV4x Reference Manual, Rev. 2, 02/2015
876
Preliminary
Freescale Semiconductor, Inc.