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To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by
dividing the IPBus clock frequency by 1-128. The prescaler bits, CTRL[PRSC], select
the prescaler divisor. This prescaler is buffered and will not be used by the PWM
generator until MCTRL[LDOK] is set and a new PWM reload cycle begins or
CTRL[LDMOD] is set.
37.5.2.2 Register Reload Logic
The register reload logic is used to determine when the outer set of registers for all double
buffered register pairs will be transferred to the inner set of registers. The register reload
event can be scheduled to occur every "n" PWM cycles using CTRL[LDFQ] and
CTRL[FULL]. A half cycle reload option is also supported (CTRL[HALF]) where the
reload can take place in the middle of a PWM cycle. The half cycle point is defined by
the VAL0 register and does not have to be exactly in the middle of the PWM cycle.
the reload signal from submodule0 can be broadcast as the
Master Reload signal allowing the reload logic from submodule0 to control the reload of
registers in other submodules.
0
1
Reload
Logic
(counts
PWM
cycles)
Local Reload
LDOK
Mod Compare
Half Compare
Master Reload
Register Reload
Master Reload
(from submod0 only)
RELOAD_SEL
Reload opportunity
(to on-chip trigger unit)
Figure 37-235. Register Reload Logic
37.5.2.3 Counter Synchronization
In the following figure, the 16 bit counter will count up until its output equals VAL1
which is used to specify the counter modulus value. The resulting compare causes a
rising edge to occur on the Local Sync signal which is one of four possible sources used
to cause the 16 bit counter to be initialized with INIT. If Local Sync is selected as the
counter initialization signal, then VAL1 within the submodule effectively controls the
timer period (and thus the PWM frequency generated by that submodule) and everything
works on a local level.
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
837
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