NXP Semiconductors freescale KV4 Series, Reference Manual

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37.4.35 Capture Value 2 Register (PWMA_SMnCVAL2)
Address: 4003_3000h base + 48h (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read CAPTVAL2
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWMA_SMnCVAL2 field descriptions
Field Description
CAPTVAL2 This read-only register stores the value captured from the submodule counter. Exactly when this capture
occurs is defined by CAPTCTRLA[EDGA0]. Each capture increases the value of CAPTCTRLA[CA0CNT]
by 1 until the maximum value is reached. Each read of this register decreases the value of
CAPTCTRLA[CA0CNT] by 1 until 0 is reached. This register is not byte accessible.
37.4.36 Capture Value 2 Cycle Register (PWMA_SMnCVAL2CYC)
Address: 4003_3000h base + 4Ah (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 CVAL2CYC
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWMA_SMnCVAL2CYC field descriptions
Field Description
15–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2. This
register is incremented each time the counter is loaded with the INIT value at the end of a PWM modulo
cycle.
37.4.37 Capture Value 3 Register (PWMA_SMnCVAL3)
Address: 4003_3000h base + 4Ch (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read CAPTVAL3
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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