NXP Semiconductors freescale KV4 Series, Reference Manual

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• Buffered receive operation using the receive FIFO (RX FIFO) with depth of 4 entries
• Asynchronous clocking scheme for Register and Protocol Interfaces
• TX and RX FIFOs can be disabled individually for low-latency updates to SPI
queues
• Visibility into TX and RX FIFOs for ease of debugging
• Programmable transfer attributes on a per-frame basis:
• two transfer attribute registers
• Serial clock (SCK) with programmable polarity and phase
• Various programmable delays
• Programmable serial frame size: 4 to 16 bits
• SPI frames longer than 16 bits can be supported using the continuous
selection format.
• Continuously held chip select capability
• 6 peripheral chip selects (PCSes), expandable to 64 with external demultiplexer
• Deglitching support for up to 32 peripheral chip selects (PCSes) with external
demultiplexer
• DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
• TX FIFO is not full (TFFF)
• RX FIFO is not empty (RFDF)
• Interrupt conditions:
• End of Queue reached (EOQF)
• TX FIFO is not full (TFFF)
• Transfer of current frame complete (TCF)
• Attempt to transmit with an empty Transmit FIFO (TFUF)
• RX FIFO is not empty (RFDF)
• Frame received while Receive FIFO is full (RFOF)
• Global interrupt request line
• Modified SPI transfer formats for communication with slower peripheral devices
• Power-saving architectural features:
Chapter 44 Serial Peripheral Interface (SPI)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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