NXP Semiconductors freescale KV4 Series, Reference Manual

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37.4.13 Value Register 4 (PWMA_SMnVAL4)
Address: 4003_3000h base + 1Ah (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
VAL4
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWMA_SMnVAL4 field descriptions
Field Description
VAL4 Value Register 4
The 16-bit signed value in this buffered, read/write register defines the count value to set PWM45 high.
This register is not byte accessible.
NOTE: The VAL4 register is buffered. The value written does not take effect until MCTRL[LDOK] is set
and the next PWM load cycle begins or CTRL[LDMOD] is set. VAL4 cannot be written when
MCTRL[LDOK] is set. Reading VAL4 reads the value in a buffer and not necessarily the value the
PWM generator is currently using.
37.4.14 Fractional Value Register 5 (PWMA_SMnFRACVAL5)
Address: 4003_3000h base + 1Ch (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
FRACVAL5
0
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWMA_SMnFRACVAL5 field descriptions
Field Description
15–11
FRACVAL5
Fractional Value 5
These bits act as a fractional addition to the value in the VAL5 register which controls the PWM_B turn off
timing. It is also used to control the fractional addition to the turn on delay of PWM_A when
MCTRL[IPOLx]=1 in complementary mode, CTRL2[INDEP]=0.
NOTE: The FRACVAL5 register is buffered. The value written does not take effect until MCTRL[LDOK] is
set and the next PWM load cycle begins or CTRL[LDMOD] is set. FRACVAL5 cannot be written
when MCTRL[LDOK] is set. Reading FRACVAL5 reads the value in a buffer and not necessarily
the value the PWM generator is currently using.
NOTE: FRCTRL[FRAC45_EN] should be set to 0 when the values of VAL4 and VAL5 cause the high or
low time of the PWM output to be 3 cycles or less.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
790
Preliminary
Freescale Semiconductor, Inc.