NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1228 / 1359

44.6.6 Calculation of FIFO pointer addresses
Complete visibility of the FIFO contents is available through the FIFO registers, and
valid entries can be identified through a memory-mapped pointer and counter for each
FIFO. The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO
the first-in pointer is the Transmit Next Pointer (TXNXTPTR). For the CMD FIFO the
first-in pointer is the Command Next Pointer (CMDNXTPTR). For the RX FIFO the
first-in pointer is the Pop Next Pointer (POPNXTPTR). The following figure illustrates
the concept of first-in and last-in FIFO entries along with the FIFO Counter. The TX
FIFO is chosen for the illustration, but the concepts carry over. See
Transmit First In First
Out (TX FIFO) buffering mechanism , Command First In First Out (CMD FIFO)
Buffering Mechanism and Receive First In First Out (RX FIFO) buffering mechanism for
details on the FIFO operation.
Push TX FIFO Register
Transmit Next
Data Pointer
Shift Register
SOUT
+1
-1
TX FIFO Counter
TX FIFO Base
-
Entry C
Entry A (first in)
Entry D (last in)
Entry B
-
-
-
Figure 44-41. TX FIFO pointers and counter
44.6.6.1 Address Calculation for the First-in Entry and Last-in Entry
in the TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following
equation:
Initialization/application information
KV4x Reference Manual, Rev. 2, 02/2015
1228
Preliminary
Freescale Semiconductor, Inc.