NXP Semiconductors freescale KV4 Series, Reference Manual

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34.4.11 ADC Ready Register (ADC_RDY)
This register provides the current status of the ADC conversions. RDY[RDYx] bits are
cleared by reading their corresponding result registers (RSLTx).
Address: 4005_C000h base + 14h offset = 4005_C014h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read RDY[15:0]
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_RDY field descriptions
Field Description
RDY[15:0] Ready Sample
These bits indicate samples fifteen through zero are ready to be read. These bits are cleared after a read
from the respective results register. The RDY[RDYn] bits are set as the individual channel conversions are
completed. Polling the RDY[RDYn] bits can determine if a particular sample is ready to be read.
0 Sample not ready or has been read
1 Sample ready to be read
34.4.12 ADC Low Limit Status Register (ADC_LOLIMSTAT)
The low limit status register latches in the result of the comparison between the result of
the sample and the respective low limit register, LOLIM0-15. Here is an example: If the
result for the channel programmed in CLIST1[SAMPLE0] is lower than the value
programmed into the Low Limit Register zero, then the LIMSTAT[LLS0] bit is set to
one. An interrupt is generated if the CTRL1[LLMTIE] bit is set. These bits are sticky.
They are not cleared automatically by subsequent conversions. Each bit is cleared only by
writing a value of one to that specific bit.
Address: 4005_C000h base + 16h offset = 4005_C016h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read LLS[15:0]
Write w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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