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NOTE
The INIT register is buffered. The value written does not take
effect until MCTRL[LDOK] is set and the next PWM load
cycle begins or CTRL[LDMOD] is set. This register cannot be
written when MCTRL[LDOK] is set. Reading INIT reads the
value in a buffer and not necessarily the value the PWM
generator is currently using.
Address: 4003_3000h base + 2h (96d × i), where i=0d to 3d
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWMA_SMnINIT field descriptions
Field
Description
INIT
Initial Count Register Bits
37.4.3 Control 2 Register (PWMA_SMnCTRL2)
Address: 4003_3000h base + 4h (96d × i), where i=0d to 3d
Bit
15
14
13
12
11
10
9
8
Read
Write
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
0
Write
Reset
0
0
0
0
0
0
0
0
PWMA_SMnCTRL2 field descriptions
Field
Description
15
DBGEN
Debug Enable
When set to one, the PWM will continue to run while the chip is in debug mode. If the device enters debug
mode and this bit is zero, then the PWM outputs will be disabled until debug mode is exited. At that point
the PWM pins will resume operation as programmed in the PWM registers.
For certain types of motors (such as 3-phase AC), it is imperative that this bit be left in its default state (in
which the PWM is disabled in debug mode). Failure to do so could result in damage to the motor or
inverter. For other types of motors (example: DC motors), this bit might safely be set to one, enabling the
PWM in debug mode. The key point is PWM parameter updates will not occur in debug mode. Any motors
requiring such updates should be disabled during debug mode. If in doubt, leave this bit set to zero.
Table continues on the next page...
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
781
Summary of Contents for freescale KV4 Series
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