NXP Semiconductors freescale KV4 Series, Reference Manual

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PDBx_CHnC1 field descriptions (continued)
Field Description
set of configuration and results registers. Application code must enable only the back-to-back operation of
the PDB pre-triggers at the leading of the back-to-back connection chain.
0 PDB channel's corresponding pre-trigger back-to-back operation disabled.
1 PDB channel's corresponding pre-trigger back-to-back operation enabled.
15–8
TOS
PDB Channel Pre-Trigger Output Select
These bits select the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this
MCU.
0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral
clock cycle after a rising edge is detected on selected trigger input source or software trigger is
selected and SWTRIG is written with 1.
1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register
plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or
software trigger is selected and SETRIG is written with 1.
EN PDB Channel Pre-Trigger Enable
Enables the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are implemented in this MCU.
0 PDB channel's corresponding pre-trigger disabled.
1 PDB channel's corresponding pre-trigger enabled.
38.4.6 Channel n Status register (PDBx_CHnS)
Address: Base a 14h (40d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CF
0
ERR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnS field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
CF
PDB Channel Flags
The CF[ m ] field is set when the PDB counter matches the CH n DLY m . Write 0 to clear these bits.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
ERR PDB Channel Sequence Error Flags
Only the lower M bits are implemented in this MCU.
0 Sequence error not detected on PDB channel's corresponding pre-trigger.
1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered
for a conversion by one pre-trigger from PDB channel
n . When one conversion, which is triggered by
Table continues on the next page...
Chapter 38 Programmable Delay Block (PDB)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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