The BUF7I to BUF5I flags are also used to represent FIFO interrupts when the Rx FIFO
is enabled. When the bit CAN_MCR[RFEN] is set and the bit CAN_MCR[DMA] is
negated, the function of the 8 least significant interrupt flags changes: BUF7I, BUF6I and
BUF5I indicate operating conditions of the FIFO, BUF0I is used to empty FIFO, and
BUF4I to BUF1I bits are reserved.
Before enabling the CAN_MCR[RFEN], the CPU must service the IFLAG bits asserted
in the Rx FIFO region; see Section "Rx FIFO". Otherwise, these IFLAG bits will
mistakenly show the related MBs now belonging to FIFO as having contents to be
serviced. When the CAN_MCR[RFEN] bit is negated, the FIFO flags must be cleared.
The same care must be taken when an CAN_CTRL2[RFFN] value is selected extending
Rx FIFO filters beyond MB7. For example, when RFFN is 0x8, the MB0-23 range is
occupied by Rx FIFO filters and related IFLAG bits must be cleared.
When both the CAN_MCR[RFEN] and CAN_MCR[DMA] bits are asserted (DMA
feature for Rx FIFO enabled), the function of the 8 least significant interrupt flags
(BUF7I - BUF0I) are changed to support the DMA operation. BUF7I and BUF6I are not
used, as well as, BUF4I to BUF1I. BUF5I indicates operating condition of FIFO, and
BUF0I is used to empty FIFO. Moreover, BUF5I does not generate a CPU interrupt, but
generates a DMA request. IMASK1 bits in Rx FIFO region are not considered when bit
CAN_MCR[DMA] is enabled. In addition the CPU must not clear the flag BUF5I when
DMA is enabled. Before enabling the bit CAN_MCR[DMA], the CPU must service the
IFLAGs asserted in the Rx FIFO region. When the bit CAN_MCR[DMA] is negated, the
FIFO must be empty.
Before updating CAN_MCR[MAXMB] field, CPU must service the CAN_IFLAG1 bits
whose MB value is greater than the CAN_MCR[MAXMB] to be updated; otherwise,
they will remain set and be inconsistent with the number of MBs available.
Address: Base a 30h offset
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1109
Summary of Contents for freescale KV4 Series
Page 2: ...KV4x Reference Manual Rev 2 02 2015 2 Preliminary Freescale Semiconductor Inc...
Page 60: ...KV4x Reference Manual Rev 2 02 2015 60 Preliminary Freescale Semiconductor Inc...
Page 128: ...Debug Security KV4x Reference Manual Rev 2 02 2015 128 Preliminary Freescale Semiconductor Inc...
Page 138: ...Boot KV4x Reference Manual Rev 2 02 2015 138 Preliminary Freescale Semiconductor Inc...
Page 1358: ...KV4x Reference Manual Rev 2 02 2015 1358 Preliminary Freescale Semiconductor Inc...
