NXP Semiconductors freescale KV4 Series, Reference Manual

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CANx_ESR1 field descriptions (continued)
Field Description
0 No such occurrence.
1 Indicates a recessive to dominant transition was received on the CAN bus.
43.4.10 Interrupt Masks 1 register (CANx_IMASK1)
This register allows any number of a range of the 16 Message Buffer Interrupts to be
enabled or disabled for MB15 to MB0. It contains one interrupt mask bit per buffer,
enabling the CPU to determine which buffer generates an interrupt after a successful
transmission or reception, that is, when the corresponding CAN_IFLAG1 bit is set.
Address: Base a 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUF31TO0M
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_IMASK1 field descriptions
Field Description
BUF31TO0M Buffer MB
i
Mask
Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB31 to MB0.
NOTE: Setting or clearing a bit in the CAN_IMASK1 Register can assert or negate an interrupt request, if
the corresponding IFLAG1 bit is set.
0 The corresponding buffer Interrupt is disabled.
1 The corresponding buffer Interrupt is enabled.
43.4.11 Interrupt Flags 1 register (CANx_IFLAG1)
This register defines the flags for the16 Message Buffer interrupts for MB15 to MB0. It
contains one interrupt flag bit per buffer. Each successful transmission or reception sets
the corresponding CAN_IFLAG1 bit. If the corresponding CAN_IMASK1 bit is set, an
interrupt will be generated. The interrupt flag must be cleared by writing 1 to it. Writing 0
has no effect. There is an exception when DMA for Rx FIFO is enabled, as described
below.
Memory map/register definition
KV4x Reference Manual, Rev. 2, 02/2015
1108
Preliminary
Freescale Semiconductor, Inc.