NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 791 / 1359

37.4.15 Value Register 5 (PWMA_SMnVAL5)
Address: 4003_3000h base + 1Eh (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
VAL5
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWMA_SMnVAL5 field descriptions
Field Description
VAL5 Value Register 5
The 16-bit signed value in this buffered, read/write register defines the count value to set PWM45 low.
This register is not byte accessible.
NOTE: The VAL5 register is buffered. The value written does not take effect until MCTRL[LDOK] is set
and the next PWM load cycle begins or CTRL[LDMOD] is set. VAL5 cannot be written when
MCTRL[LDOK] is set. Reading VAL5 reads the value in a buffer and not necessarily the value the
PWM generator is currently using.
37.4.16 Fractional Control Register (PWMA_SMnFRCTRL)
Address: 4003_3000h base + 20h (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8
Read TEST 0
FRAC_PU
Write
Reset
0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read 0
FRAC45_
EN
0
FRAC23_
EN
FRAC1_EN
0
Write
Reset 0 0 0 0 0 0 0 0
PWMA_SMnFRCTRL field descriptions
Field Description
15
TEST
Test Status Bit
This is a read only test bit for factory use. This bit will reset to 0 but may be either 0 or 1 during PWM
operation.
14–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
FRAC_PU
Fractional Delay Circuit Power Up
This bit is used to power up the fractional delay analog block. The fractional delay block takes 25 us to
power up after the first FRAC_PU bit in any submodule is set. The fractional delay block only powers
Table continues on the next page...
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
791