NXP Semiconductors freescale KV4 Series, Reference Manual

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SPI_SR field descriptions (continued)
Field Description
17
RFDF
Receive FIFO Drain Flag
Provides a method for the module to request that entries be removed from the RX FIFO. The bit is set
while the RX FIFO is not empty. The RFDF bit can be cleared by writing 1 to it or by acknowledgement
from the DMA controller when the RX FIFO is empty.
0 RX FIFO is empty.
1 RX FIFO is not empty.
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–12
TXCTR
TX FIFO Counter
Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented every time the PUSHR is
written. The TXCTR is decremented every time an SPI command is executed and the SPI data is
transferred to the shift register.
11–8
TXNXTPTR
Transmit Next Pointer
Indicates which TX FIFO entry is transmitted during the next transfer. The TXNXTPTR field is updated
every time SPI data is transferred from the TX FIFO to the shift register.
7–4
RXCTR
RX FIFO Counter
Indicates the number of entries in the RX FIFO. The RXCTR is decremented every time the POPR is read.
The RXCTR is incremented every time data is transferred from the shift register to the RX FIFO.
POPNXTPTR Pop Next Pointer
Contains a pointer to the RX FIFO entry to be returned when the POPR is read. The POPNXTPTR is
updated when the POPR is read.
Memory Map/Register Definition
KV4x Reference Manual, Rev. 2, 02/2015
1192
Preliminary
Freescale Semiconductor, Inc.