NXP Semiconductors freescale KV4 Series, Reference Manual

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independently. Each converter has its own start, stop, sync, end-of-scan interrupt enable
controls, and interrupts. Scanning in either converter terminates only when that converter
encounters a disabled sample.
The ADC can be configured to perform a single scan and halt, perform a scan whenever
triggered, or perform the scan sequence repeatedly until manually stopped. The single
scan (once mode) differs from the triggered mode only in that SYNC input signals must
be re-armed after each use and subsequent SYNC inputs are ignored until the SYNC
input is re-armed. This arming can occur any time after the SYNC pulse, including while
the scan is still in process.
Optional interrupts can be generated at the end of a scan sequence. Interrupts are
available simply to indicate that a scan has ended, that a sample is out of range, or several
different zero crossing conditions. Range is determined by the high and low limit
registers.
34.5.1 Input Multiplex Function
The following figure shows the input multiplex function. The ChannelSelect and
SingleEndedDifferential switches are indirectly controlled by settings within the
following registers:
• CLIST1, CLIST2, CLIST3, CLIST4, and SDIS registers
• CTRL1[CHNCFG_L]
• CTRL2[CHNCFG_H]
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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