NXP Semiconductors freescale KV4 Series, Reference Manual

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MCG_C5 field descriptions (continued)
Field Description
Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled even if
PLLSTEN=1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL Clock to
run if it is written to 1.
0 MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes.
1
MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode.
4–3
Reserved
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
PRDIV PLL External Reference Divider
Selects the amount to divide down the external reference clock for the PLL0. The resulting frequency must
be in the range of 8 MHz to 16 MHz. After the PLL0 is enabled (by setting either PLLCLKEN0 or PLLS),
the PRDIV0 value must not be changed when LOCK0 is zero.
Table 30-7. PLL External Reference Divide Factor
PRDIV Divide Factor
000 1
001 2
010 3
011 4
100 5
101 6
110 7
111 8
30.3.6 MCG Control 6 Register (MCG_C6)
Address: 4006_4000h base + 5h offset = 4006_4005h
Bit 7 6 5 4 3 2 1 0
Read
LOLIE0 PLLS CME0 VDIV
Write
Reset 0 0 0 0 0 0 0 0
MCG_C6 field descriptions
Field Description
7
LOLIE0
Loss of Lock Interrrupt Enable
Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect
when LOLS 0 is set.
Table continues on the next page...
Chapter 30 Multipurpose Clock Generator (MCG)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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