NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1327 / 1359

Chapter 47
General-Purpose Input/Output (GPIO)
Chip-specific GPIO information
47.1.1 GPIO access protection
The GPIO module does not have access protection because it is not connected to a
peripheral bridge slot.
47.1.2 Number of GPIO signals
The number of GPIO signals available on the devices covered by this document are
detailed in
Orderable part numbers .
Eight GPIO pins support a high drive capability - PTB0, PTB1, PTD4, PTD5, PTD6,
PTD7, PTC3, and PTC4. All other GPIO support normal drive option only.
PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE]
control. This reset default is to have this function disabled.
PTC6 and PTC7 have true open-drain outputs thus when enabled as outputs, an external
pull-resistor is required if output is logic 1.
47.2 Introduction
The GPIO registers support 8-bit, 16-bit or 32-bit accesses.
The GPIO data direction and output data registers control the direction and output data of
each pin when the pin is configured for the GPIO function. The GPIO input data register
displays the logic value on each pin when the pin is configured for any digital function,
provided the corresponding Port Control and Interrupt module for that pin is enabled.
47.1
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1327