NXP Semiconductors freescale KV4 Series, Reference Manual

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43.5.7 Rx FIFO
The Rx FIFO is receive-only and is enabled by asserting the CAN_MCR[RFEN] bit. The
reset value of this bit is zero to maintain software backward compatibility with previous
versions of the module that did not have the FIFO feature.
The FIFO is 6-message deep. The memory region occupied by the FIFO structure (both
Message Buffers and FIFO engine) is described in
Rx FIFO structure . The CPU can read
the received messages sequentially, in the order they were received, by repeatedly
reading a Message Buffer structure at the output of the FIFO.
The CAN_IFLAG1[BUF5I] (Frames available in Rx FIFO) is asserted when there is at
least one frame available to be read from the FIFO. An interrupt is generated if it is
enabled by the corresponding mask bit. Upon receiving the interrupt, the CPU can read
the message (accessing the output of the FIFO as a Message Buffer) and the
CAN_RXFIR register and then clear the interrupt. If there are more messages in the FIFO
the act of clearing the interrupt updates the output of the FIFO with the next message and
update the CAN_RXFIR with the attributes of that message, reissuing the interrupt to the
CPU. Otherwise, the flag remains negated. The output of the FIFO is only valid whilst
the CAN_IFLAG1[BUF5I] is asserted.
The CAN_IFLAG1[BUF6I] (Rx FIFO Warning) is asserted when the number of unread
messages within the Rx FIFO is increased to 5 from 4 due to the reception of a new one,
meaning that the Rx FIFO is almost full. The flag remains asserted until the CPU clears
it.
The CAN_IFLAG1[BUF7I] (Rx FIFO Overflow) is asserted when an incoming message
was lost because the Rx FIFO is full. Note that the flag will not be asserted when the Rx
FIFO is full and the message was captured by a Mailbox. The flag remains asserted until
the CPU clears it.
Clearing one of those three flags does not affect the state of the other two.
An interrupt is generated if an IFLAG bit is asserted and the corresponding mask bit is
asserted too.
A powerful filtering scheme is provided to accept only frames intended for the target
application, reducing the interrupt servicing work load. The filtering criteria is specified
by programming a table of up to 128 32-bit registers, according to CAN_CTRL2[RFFN]
setting, that can be configured to one of the following formats (see also
Rx FIFO
structure ):
• Format A: 128 IDAFs (extended or standard IDs including IDE and RTR)
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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