NXP Semiconductors freescale KV4 Series, Reference Manual

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Table 43-108. DATA BYTEs validity (continued)
DLC Valid DATA BYTEs
5 DATA BYTE 0 to 4
6 DATA BYTE 0 to 5
7 DATA BYTE 0 to 6
8 or above DATA BYTE 0 to 7
43.4.54 Rx FIFO structure
When the CAN_MCR[RFEN] bit is set, the memory area from 0x80 to 0xDC (which is
normally occupied by MBs 0–5) is used by the reception FIFO engine.
The region 0x80-0x8C contains the output of the FIFO which must be read by the CPU as
a message buffer. This output contains the oldest message that has been received but not
yet read. The region 0x90-0xDC is reserved for internal use of the FIFO engine.
An additional memory area, which starts at 0xE0 and may extend up to 0x17C (normally
occupied by MBs 6–15) depending on the CAN_CTRL2[RFFN] field setting, contains
the ID filter table (configurable from 8 to 40 table elements) that specifies filtering
criteria for accepting frames into the FIFO.
Out of reset, the ID filter table flexible memory area defaults to 0xE0 and extends only to
0xFC, which corresponds to MBs 6 to 7 for RFFN = 0, for backward compatibility with
previous versions of FlexCAN.
The following shows the Rx FIFO data structure.
Table 43-109. Rx FIFO structure
31 28 24 23 22 21 20 19 18 17 16 15 8 7 0
0x80 IDHIT SRR IDE RTR DLC TIME STAMP
0x84 ID standard ID extended
0x88 Data byte 0 Data byte 1 Data byte 2 Data byte 3
0x8C Data byte 4 Data byte 5 Data byte 6 Data byte 7
0x90
to
0xDC
Reserved
0xE0 ID filter table element 0
0xE4 ID filter table element 1
0xE8
to
0x2D4
ID filter table elements 2 to 125
Table continues on the next page...
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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