NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1094 / 1359

CANx_CTRL1 field descriptions (continued)
Field Description
This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency.
The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock
frequency is equal to the PE clock frequency. The Maximum value of this field is 0xFF, that gives a
minimum Sclock frequency equal to the PE clock frequency divided by 256. See Section "Protocol
Timing". This field can be written only in Freeze mode because it is blocked by hardware in other modes.
Sclock frequency = PE clock frequency / (P 1)
23–22
RJW
Resync Jump Width
This 2-bit field defines the maximum number of time quanta that a bit time can be changed by one re-
synchronization. One time quantum is equal to the Sclock period. The valid programmable values are 0–3.
This field can be written only in Freeze mode because it is blocked by hardware in other modes.
Resync Jump Width = RJW + 1.
21–19
PSEG1
Phase Segment 1
This 3-bit field defines the length of Phase Segment 1 in the bit time. The valid programmable values are
0–7. This field can be written only in Freeze mode because it is blocked by hardware in other modes.
Phase Buffer Segment 1 = (PSEG1 + 1) × Time-Quanta.
18–16
PSEG2
Phase Segment 2
This 3-bit field defines the length of Phase Segment 2 in the bit time. The valid programmable values are
1–7. This field can be written only in Freeze mode because it is blocked by hardware in other modes.
Phase Buffer Segment 2 = (PSEG2 + 1) × Time-Quanta.
15
BOFFMSK
Bus Off Interrupt Mask
This bit provides a mask for the Bus Off Interrupt BOFFINT in CAN_ESR1 register.
0 Bus Off interrupt disabled.
1 Bus Off interrupt enabled.
14
ERRMSK
Error Interrupt Mask
This bit provides a mask for the Error Interrupt ERRINT in the CAN_ESR1 register.
0 Error interrupt disabled.
1 Error interrupt enabled.
13
CLKSRC
CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Engine (PE) to be either the peripheral clock or the
oscillator clock. The selected clock is the one fed to the prescaler to generate the Serial Clock (Sclock). In
order to guarantee reliable operation, this bit can be written only in Disable mode because it is blocked by
hardware in other modes. See
Protocol timing ".
0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock
frequency must be lower than the bus clock.
1 The CAN engine clock source is the peripheral clock.
12
LPB
Loop Back Mode
This bit configures FlexCAN to operate in Loop-Back mode. In this mode, FlexCAN performs an internal
loop back that can be used for self test operation. The bit stream output of the transmitter is fed back
internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
recessive state (logic 1). FlexCAN behaves as it normally does when transmitting, and treats its own
transmitted message as a message received from a remote node.
Table continues on the next page...
Memory map/register definition
KV4x Reference Manual, Rev. 2, 02/2015
1094
Preliminary
Freescale Semiconductor, Inc.