NXP Semiconductors freescale KV4 Series, Reference Manual

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• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames)
• Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload
Frame Delimiter
43.5.8.3 Time stamp
The value of the Free Running Timer is sampled at the beginning of the Identifier field on
the CAN bus, and is stored at the end of "move-in" in the TIME STAMP field, providing
network behavior with respect to time.
The Free Running Timer is clocked by the FlexCAN bit-clock, which defines the baud
rate on the CAN bus. During a message transmission/reception, it increments by one for
each bit that is received or transmitted. When there is no message on the bus, it counts
using the previously programmed baud rate.
The Free Running Timer is not incremented during Disable, Doze, Stop, and Freeze
modes. It can be reset upon a specific frame reception, enabling network time
synchronization. See the TSYN description in Control 1 Register (CAN_CTRL1).
43.5.8.4 Protocol timing
The following figure shows the structure of the clock generation circuitry that feeds the
CAN Protocol Engine (PE) submodule. The clock source bit CLKSRC in the
CAN_CTRL1 Register defines whether the internal clock is connected to the output of a
crystal oscillator (Oscillator Clock) or to the Peripheral Clock. In order to guarantee
reliable operation, the clock source should be selected while the module is in Disable
Mode (MDIS bit set in the Module Configuration Register).
CAN_CTRL1[CLKSRC]
Sclock CANCLK
Prescaler
Peripheral Clock
Oscillator Clock
(Tq)
1
0
Figure 43-101. CAN engine clocking scheme
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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