NXP Semiconductors freescale KV4 Series, Reference Manual

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UARTx_S1 field descriptions
Field Description
7
TDRE
Transmit Data Register Empty Flag
TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than
the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is not
included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data register
(D). For more efficient interrupt servicing, all data except the final value to be written to the buffer must be
written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the clearing of the
TRDE flag. This is more efficient because the TDRE reasserts until the watermark has been exceeded.
So, attempting to clear the TDRE with every write will be ineffective until sufficient data has been written.
0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
1 The amount of data in the transmit buffer is less than or equal to the value indicated by
TWFIFO[TXWATER] at some point in time since the flag has been cleared.
6
TC
Transmit Complete Flag
TC is set when the transmit buffer is empty and no data, preamble, or break character is being
transmitted. When TC is set, the transmit data output signal becomes idle (logic 1). TC is cleared by
reading S1 with TC set and then doing one of the following:
• Writing to D to transmit new data.
• Queuing a preamble by clearing and then setting C2[TE].
• Queuing a break character by writing 1 to SBK in C2.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
5
RDRF
Receive Data Register Full Flag
RDRF is set when the number of datawords in the receive buffer is equal to or more than the number
indicated by RWFIFO[RXWATER]. A dataword that is in the process of being received is not included in
the count. To clear RDRF, read S1 when RDRF is set and then read D. For more efficient interrupt and
DMA operation, read all data except the final value from the buffer, using D/C3[T8]/ED. Then read S1 and
the final data value, resulting in the clearing of the RDRF flag. Even if RDRF is set, data will continue to be
received until an overrun condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive buffer but over-write
each other.
0 The number of datawords in the receive buffer is less than the number indicated by RXWATER.
1 The number of datawords in the receive buffer is equal to or greater than the number indicated by
RXWATER at some point in time since this flag was last cleared.
4
IDLE
Idle Line Flag
After the IDLE flag is cleared, a frame must be received (although not necessarily stored in the data buffer,
for example if C2[RWU] is set), or a LIN break character must set the S2[LBKDIF] flag before an idle
condition can set the IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
IDLE is set when either of the following appear on the receiver input:
• 10 consecutive logic 1s if C1[M] = 0
• 11 consecutive logic 1s if C1[M] = 1 and C4[M10] = 0
• 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1
NOTE: When RWU is set and WAKE is cleared, an idle line condition sets the IDLE flag if RWUID is set,
else the IDLE flag does not become set.
0 Receiver input is either active now or has never become active since the IDLE flag was last cleared.
1 Receiver input has become idle or the flag has not been cleared since it last asserted.
3
OR
Receiver Overrun Flag
Table continues on the next page...
Memory map and registers
KV4x Reference Manual, Rev. 2, 02/2015
1278
Preliminary
Freescale Semiconductor, Inc.