PWMA_MCTRL field descriptions (continued)
Field
Description
11–8
RUN
Run
The four read/write bits of this field enable the clocks to the PWM generator of submodules 3-0,
respectively. The corresponding MCTRL[RUN] bit must be set for each submodule that is using its input
capture functions or is using the local reload as its reload source. When this bit equals zero, the
submodule counter is reset. A reset clears this field.
0
PWM generator is disabled in the corresponding submodule.
1
PWM generator is enabled in the corresponding submodule.
7–4
CLDOK
Clear Load Okay
The 4 bits of CLDOK field correspond to submodules 3-0, respectively. Each write-only bit is used to clear
the corresponding bit of MCTRL[LDOK]. Write a 1 to CLDOK to clear the corresponding MCTRL[LDOK]
bit. If a reload occurs within a submodule with the corresponding MCTRL[LDOK] bit set at the same time
that MCTRL[CLDOK] is written, then the reload in that submodule will not be performed and
MCTRL[LDOK] will be cleared. CLDOK bit is self-clearing and always reads as a 0.
LDOK
Load Okay
The 4 bits of LDOK field correspond to submodules 3-0, respectively. Each read/set bit loads
CTRL[PRSC] and the INIT, FRACVALx, and VALx registers of the corresponding submodule into a set of
buffers. The buffered prescaler divisor, submodule counter modulus value, and PWM pulse width take
effect at the next PWM reload if CTRL[LDMOD] is clear or immediately if CTRL[LDMOD] is set. Set the
corresponding MCTRL[LDOK] bit by reading it when it is logic zero and then writing a logic one to it. The
VALx, FRACVALx,INIT, and CTRL[PRSC] registers of the corresponding submodule cannot be written
while the the corresponding MCTRL[LDOK] bit is set.
In Master Reload Mode (CTRL2[RELOAD_SEL]=1), it is only necessary to set the LDOK bit
corresponding to submodule0; however, it is recommended to also set the LDOK bit of the slave
submodules, to prevent unwanted writes to the registers in the slave submodules.
The MCTRL[LDOK] bit is automatically cleared after the new values are loaded, or it can be manually
cleared before a reload by writing a logic 1 to the appropriate MCTRL[CLDOK] bit. LDOK bits cannot be
written with a zero. MCTRL[LDOK] can be set in DMA mode when the DMA indicates that it has
completed the update of all CTRL[PRSC], INIT,FRACVALx, and VALx registers in the corresponding
submodule. Reset clears LDOK field.
0
Do not load new values.
1
Load prescaler, modulus, and PWM values of the corresponding submodule.
37.4.49 Master Control 2 Register (PWMA_MCTRL2)
Address: 4003_3000h base + 18Ah offset = 4003_318Ah
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
820
Preliminary
Freescale Semiconductor, Inc.
Summary of Contents for freescale KV4 Series
Page 2: ...KV4x Reference Manual Rev 2 02 2015 2 Preliminary Freescale Semiconductor Inc...
Page 60: ...KV4x Reference Manual Rev 2 02 2015 60 Preliminary Freescale Semiconductor Inc...
Page 128: ...Debug Security KV4x Reference Manual Rev 2 02 2015 128 Preliminary Freescale Semiconductor Inc...
Page 138: ...Boot KV4x Reference Manual Rev 2 02 2015 138 Preliminary Freescale Semiconductor Inc...
Page 1358: ...KV4x Reference Manual Rev 2 02 2015 1358 Preliminary Freescale Semiconductor Inc...
