NXP Semiconductors freescale KV4 Series, Reference Manual

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V
IN
=Applied voltage at the input pin
V
REFH
and V
REFL
=Voltage at the external reference pins on the device (typically V
REFH
=V
DDA
and V
REFL
=V
SSA
)
Note: The 12-bit result is rounded to the nearest LSB.
Note: The ADC is a 12-bit function with 4096 possible states. However, the 12 bits have been left shifted three bits on the
16-bit data bus, so the magnitude of this function, as read from the data bus, is now 32760.
+
- -
V
REFH
Potential
AN+
AN–
AN+
AN–
Note: Normally, VREFL is set to VSSA = 0 V.
Differential buffer centers about mid-point.
Center tap held at (V
REFH
+ V
REFL
)/2.
V
REF
/2
Figure 34-98. Typical Connections for Differential Measurements
34.5.3 ADC Data Processing
The result of an ADC conversion process is normally sent to an adder for offset
correction, as the following figure shows. The adder subtracts the ADC_OFFST register
value from each sample, and the resultant value is stored in the result register (RSLT).
The raw ADC value and the RSLT values are checked for limit violations and zero-
crossing, as shown. Appropriate interrupts are asserted, if enabled.
The result value sign is determined from the ADC unsigned result minus the respective
offset register value. If the offset register is programmed with a value of zero, the result
register value is unsigned and equals the cyclic converter unsigned result. The range of
the result (RSLT) is 0000H–7FF8H, assuming that the offset register (OFFST) is cleared
to all zeros. This is equal to the raw value of the ADC core.
The processor can write the result registers used for the results of a scan when the STOP
bit for that scan is asserted. This write operation is treated as if it comes from the ADC
analog core, so the limit checking, zero crossing, and the offset registers function as if in
Functional Description
KV4x Reference Manual, Rev. 2, 02/2015
712
Preliminary
Freescale Semiconductor, Inc.