NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 193 / 1359

SIM_SCGC6 field descriptions (continued)
Field Description
22
PDB0
PDB0 Clock Gate Control
This bit controls the clock gate to the PDB0 module.
0 Clock disabled
1 Clock enabled
21–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18
CRC
CRC Clock Gate Control
This bit controls the clock gate to the CRC module.
0 Clock disabled
1 Clock enabled
17
PDB1
PDB1 Clock Gate Control
This bit controls the clock gate to the PDB1 module.
0 Clock disabled
1 Clock enabled
16–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
SPI0
SPI0 Clock Gate Control
This bit controls the clock gate to the SPI0 module.
0 Clock disabled
1 Clock enabled
11–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
FTM3
FTM3 Clock Gate Control
This bit controls the clock gate to the FTM3 module.
0 Clock disabled
1 Clock enabled
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
FLEXCAN0
FlexCAN0 Clock Gate Control
This bit controls the clock gate to the FlexCAN0 module.
0 Clock disabled
1 Clock enabled
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
DMAMUX
DMA Mux Clock Gate Control
This bit controls the clock gate to the DMA Mux module.
Table continues on the next page...
Chapter 13 System Integration Module (SIM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
193