NXP Semiconductors freescale KV4 Series, Reference Manual

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UARTx_CFIFO field descriptions (continued)
Field Description
6
RXFLUSH
Receive FIFO/Buffer Flush
Writing to this field causes all data that is stored in the receive FIFO/buffer to be flushed. This does not
affect data that is in the receive shift register.
0 No flush operation occurs.
1 All data in the receive FIFO/buffer is cleared out.
5–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
RXOFE
Receive FIFO Overflow Interrupt Enable
When this field is set, the RXOF flag generates an interrupt to the host.
0 RXOF flag does not generate an interrupt to the host.
1 RXOF flag generates an interrupt to the host.
1
TXOFE
Transmit FIFO Overflow Interrupt Enable
When this field is set, the TXOF flag generates an interrupt to the host.
0 TXOF flag does not generate an interrupt to the host.
1 TXOF flag generates an interrupt to the host.
0
RXUFE
Receive FIFO Underflow Interrupt Enable
When this field is set, the RXUF flag generates an interrupt to the host.
0 RXUF flag does not generate an interrupt to the host.
1 RXUF flag generates an interrupt to the host.
46.4.17 UART FIFO Status Register (UARTx_SFIFO)
This register provides status information regarding the transmit and receiver buffers/
FIFOs, including interrupt information. This register may be written to or read at any
time.
Address: Base a 12h offset
Bit 7 6 5 4 3 2 1 0
Read TXEMPT RXEMPT 0 RXOF TXOF RXUF
Write w1c w1c w1c
Reset 1 1 0 0 0 0 0 0
UARTx_SFIFO field descriptions
Field Description
7
TXEMPT
Transmit Buffer/FIFO Empty
Asserts when there is no data in the Transmit FIFO/buffer. This field does not take into account data that
is in the transmit shift register.
Table continues on the next page...
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1291