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27.3 Memory Map and Register Descriptions
This section provides information about the XBARB instance of the inter-peripheral
crossbar switch. Refer to the
for information about that instance
of the module.
This XBAR module has only select registers.
In the XBAR select registers, the SELn fields select which of the shared inputs
(XBAR_IN[*]) is muxed to each mux output (XBAR_OUT[*]). There is one SELn field
per mux and therefore one per XBAR_OUT output. Crossbar output XBAR_OUT[n]
presents the value of XBAR_IN[SELn]. Each select register contains two SELn fields. In
the first select register, the LSBs contain the select field for mux 0, and the MSBs contain
the select field for mux 1. The pattern repeats in subsequent select registers.
The actual signals connected to XBAR_IN and XBAR_OUT are application specific and
are described in the Chip Configuration details.
XBARB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4005_A000 Crossbar B Select Register 0 (XBARB_SEL0)
16
R/W
0000h
4005_A002 Crossbar B Select Register 1 (XBARB_SEL1)
16
R/W
0000h
4005_A004 Crossbar B Select Register 2 (XBARB_SEL2)
16
R/W
0000h
4005_A006 Crossbar B Select Register 3 (XBARB_SEL3)
16
R/W
0000h
4005_A008 Crossbar B Select Register 4 (XBARB_SEL4)
16
R/W
0000h
4005_A00A Crossbar B Select Register 5 (XBARB_SEL5)
16
R/W
0000h
4005_A00C Crossbar B Select Register 6 (XBARB_SEL6)
16
R/W
0000h
4005_A00E Crossbar B Select Register 7 (XBARB_SEL7)
16
R/W
0000h
27.3.1 Crossbar B Select Register 0 (XBARB_SEL0)
Address: 4005_A000h base + 0h offset = 4005_A000h
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
515
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