NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 141 / 1359

11.4 Signal multiplexing constraints
1. A given peripheral function must be assigned to a maximum of one package pin. Do
not program the same function to more than one pin.
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in
closest proximity to each other.
11.5 KV4x Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The 48-pin LQFP package for this product is not yet available.
However, it is included in a Package Your Way program for
Kinetis MCUs. Visit
freescale.com/KPYW for more details.
100
LQFP
64
LQFP
48
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
— 126 B5 PTC19 DISABLED PTC19 UART3_CTS_
b ENET0_1588_
TMR3 FLEXPWMB_
B3
— 134 M10 VSS DISABLED VSS
— 135 F8 VDD DISABLED VDD
— 137 C9 PTD8/
LLWU_P24 DISABLED PTD8/
LLWU_P24 I2C1_SCL UART5_RX FLEXPWMA_
A3
— 138 B9 PTD9 DISABLED PTD9 I2C1_SDA UART5_TX FLEXPWMA_
B3
— 139 B3 PTD10 DISABLED PTD10 UART5_RTS_
b FLEXPWMA_
A2
— 140 B2 PTD11/
LLWU_P25 DISABLED PTD11/
LLWU_P25 SPI2_PCS0 UART5_CTS_
b FLEXPWMA_
B2
— 141 B1 PTD12 DISABLED PTD12 SPI2_SCK FTM3_FLT0 XBAR0_IN5 XBAR0_OUT5 FLEXPWMA_
A1
— 142 C3 PTD13 DISABLED PTD13 SPI2_SOUT XBAR0_IN7 XBAR0_OUT7 FLEXPWMA_
B1
— 143 C2 PTD14 DISABLED PTD14 SPI2_SIN XBAR0_IN11 XBAR0_
OUT11 FLEXPWMA_
A0
— 144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 FLEXPWMA_
B0
1 1 — PTE0/
CLKOUT32K ADCB_CH6f ADCB_CH6f PTE0/
CLKOUT32K UART1_TX XBAR0_
OUT10 XBAR0_IN11
2 2 — PTE1/
LLWU_P0 ADCB_CH7f ADCB_CH7f PTE1/
LLWU_P0 UART1_RX XBAR0_
OUT11 XBAR0_IN7
Chapter 11 Signal Multiplexing
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
141