Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CANx_IFLAG1 field descriptions
Field
Description
31–8
BUF31TO8I
Buffer MB
i
Interrupt
Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB15 to MB8.
0
The corresponding buffer has no occurrence of successfully completed transmission or reception.
1
The corresponding buffer has successfully completed transmission or reception.
7
BUF7I
Buffer MB7 Interrupt Or "Rx FIFO Overflow"
When the RFEN bit in the CAN_MCR register is cleared (Rx FIFO disabled), this bit flags the interrupt for
MB7.
NOTE: This flag is cleared by the FlexCAN whenever the bit CAN_MCR[RFEN] is changed by CPU
writes.
The BUF7I flag represents "Rx FIFO Overflow" when CAN_MCR[RFEN] is set. In this case, the flag
indicates that a message was lost because the Rx FIFO is full. Note that the flag will not be asserted when
the Rx FIFO is full and the message was captured by a Mailbox.
0
No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO
overflow when MCR[RFEN]=1
1
MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when
MCR[RFEN]=1
6
BUF6I
Buffer MB6 Interrupt Or "Rx FIFO Warning"
When the RFEN bit in the CAN_MCR register is cleared (Rx FIFO disabled), this bit flags the interrupt for
MB6.
NOTE: This flag is cleared by the FlexCAN whenever the bit CAN_MCR[RFEN] is changed by CPU
writes.
The BUF6I flag represents "Rx FIFO Warning" when CAN_MCR[RFEN] is set. In this case, the flag
indicates when the number of unread messages within the Rx FIFO is increased to 5 from 4 due to the
reception of a new one, meaning that the Rx FIFO is almost full. Note that if the flag is cleared while the
number of unread messages is greater than 4, it does not assert again until the number of unread
messages within the Rx FIFO is decreased to be equal to or less than 4.
0
No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost
full when MCR[RFEN]=1
1
MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when
MCR[RFEN]=1
5
BUF5I
Buffer MB5 Interrupt Or "Frames available in Rx FIFO"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB5.
Table continues on the next page...
Memory map/register definition
KV4x Reference Manual, Rev. 2, 02/2015
1110
Preliminary
Freescale Semiconductor, Inc.
Summary of Contents for freescale KV4 Series
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