• SOFTRST bit in MCR, which resets some of the memory mapped registers
synchronously. See
to see what registers are affected by soft reset.
• MCU level soft reset, which has the same effect as the SOFTRST bit in MCR
Soft reset is synchronous and has to follow an internal request/acknowledge procedure
across clock domains. Therefore, it may take some time to fully propagate its effects. The
CAN_MCR[SOFTRST] bit remains asserted while soft reset is pending, so software can
poll this bit to know when the reset has completed. Also, soft reset can not be applied
while clocks are shut down in a low power mode. The low power mode should be exited
and the clocks resumed before applying soft reset.
The clock source should be selected while the module is in Disable mode (see
CAN_CTRL1[CLKSRC] bit). After the clock source is selected and the module is
enabled (CAN_MCR[MDIS] bit negated), FlexCAN automatically goes to Freeze mode.
In Freeze mode, FlexCAN is un-synchronized to the CAN bus, the HALT and FRZ bits
in CAN_MCR Register are set, the internal state machines are disabled and the FRZACK
and NOTRDY bits in the CAN_MCR Register are set. The Tx pin is in recessive state
and FlexCAN does not initiate any transmission or reception of CAN frames. Note that
the Message Buffers and the Rx Individual Mask Registers are not affected by reset, so
they are not automatically initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze
mode (see
). The following is a generic initialization sequence applicable to
the FlexCAN module:
• Initialize the Module Configuration Register (CAN_MCR)
• Enable the individual filtering per MB and reception queue features by setting
the IRMQ bit
• Enable the warning interrupts by setting the WRNEN bit
• If required, disable frame self reception by setting the SRXDIS bit
• Enable the Rx FIFO by setting the RFEN bit
• If Rx FIFO is enabled and DMA is required, set DMA bit
• Enable the abort mechanism by setting the AEN bit
• Enable the local priority feature by setting the LPRIOEN bit
• Initialize the Control 1 Register (CAN_CTRL1) and optionally the CAN Bit Timing
Register (CAN_CBT).
• Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
Initialization/application information
KV4x Reference Manual, Rev. 2, 02/2015
1166
Preliminary
Freescale Semiconductor, Inc.
Summary of Contents for freescale KV4 Series
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